Analog Devices AD9912 Uživatelský manuál stáhnout pdf (Strana 29)

AD9912

Rev. D | Page 29 of 40

06763-048

CSB

SCLK

SDIO

HIGH

LOW

CLK

BIT N BIT N + 1

Figure 56. Serial Control Port Timing—Write

Table 11. Definitions of Terms Used in Serial Control Port Timing Diagrams

Parameter Description

CLK

Period of SCLK

Read data valid time (time from falling edge of SCLK to valid data on SDIO/SDO)

Setup time between data and rising edge of SCLK

Hold time between data and rising edge of SCLK

Setup time between CSB and SCLK

Hold time between CSB and SCLK

Minimum period that SCLK should be in a logic high state

Minimum period that SCLK should be in a logic low state

1 2 ... 24 25 26 27 28 29 30 31 32 33 34 ... 39 40

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Analog Devices AD9912 Uživatelský manuál Strana 29